1. Field of the Invention
The invention relates generally to a semiconductor device and a method of fabricating the same, and more particularly, to the structure of a semiconductor device provided with an N channel MOS device and a P channel MOS device, or a MONOS device in addition thereto which are all formed on top of a common semiconductor substrate, or a common SOI substrate, and a method of fabricating the same.
2. Description of the related Art
A MOS (Metal-Oxide-Semiconductor) device using a semiconductor substrate made of silicon, and the same using a semiconductor substrate having a semiconductor layer on top of an insulating layer formed on a supporting substrate, a so-called SOI (Silicon on Insulator) substrate are well known.
First, the structure of a conventional MOS device using a semiconductor substrate made of silicon is described by way of example with reference to a schematic cross sectional view shown in FIG. 69.
The MOS device shown in FIG. 69 comprises an N channel MOS device 11, and a P channel MOS device 12, which are both formed on a semiconductor substrate 1 made of silicon, making up a complementary MOS device.
The N channel MOS device 11 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over a P well 4 formed of a p-type doped layer diffused in the semiconductor substrate 1, and also with a source 6 and drain 7, formed of a heavily doped n-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The P channel MOS device 12 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over an N well 5 formed of an n-type doped layer diffused in the semiconductor substrate 1, and also with a source 16 and drain 17, formed of a heavily doped p-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The N channel MOS device 11 and P channel MOS device 12 are isolated from each other by a field oxide film 13 formed on the surface of the semiconductor substrate 1.
An interlevel insulator 8 is formed on the entire surface of the semiconductor substrate 1, and via contact holes 9 formed in the interlevel insulator 8, connection to other MOS devices formed on the semiconductor substrate 1 is made with interconnections 10 (interconnection 10 connected to the gate electrodes 3, 3, respectively, is disposed at a position different in cross-sectional view from that shown in FIG. 69), one end of which are connected to the gate electrode 3, source 6 and drain 7 of the N channel MOS device 11 as well as the gate electrode 3, source 16 and drain 17 of the P channel MOS device 12, respectively.
Now the structure of a conventional MOS device using a SOI substrate is described by way of example with reference to a schematic cross sectional view shown in FIG. 70.
The MOS device shown in FIG. 70 makes use of the SOI substrate 23 comprising a supporting substrate 20, an insulating film 21, and a plurality of semiconductor layers 22a, 22b, each patterned in an island-like shape
A gate oxide film 2 and gate electrode 3 are formed on top of the respective semiconductor layers 22a, and 22b, making up a semiconductor device comprising an N channel MOS device 11 and a P channel MOS device 12.
The N channel MOS device 11 is provided with a source 6 and drain 7, formed of a heavily doped N type layer, in a region of the semiconductor layer 22a, matching a gate electrode 3.
Similarly, the P channel MOS device 12 is provided with a source 16 and drain 17, formed of a heavily doped P type layer, in a region of the semiconductor layer 22b, matching a gate electrode 3.
The N channel MOS device 11 and the P channel MOS device 12 are completely isolated for insulation from each other with an interlevel insulator 8 and the insulating film 21.
Then, via respective contact holes 9 formed in the interlevel insulator 8, connection to other MOS devices formed on the SOI substrate 23 is made with interconnections 10 (interconnection 10 connected to the gate electrodes 3, 3, respectively, is disposed at a position different in cross-sectional view from that shown in FIG. 70), one end of which is connected to the gate electrode 3, source 6 and drain 7 of the N channel MOS device 11 as well as the gate electrode 3, source 16 and drain 17 of the P channel MOS device 12, respectively.
Next, the structure of a conventional semiconductor device incorporating a MONOS device in addition to the semiconductor device shown in FIG. 69 is described by way of example with reference to FIG. 71.
In the semiconductor device shown in FIG. 71, an N channel MOS device 11, a P channel MOS device 12, and a MONOS device 35 are formed on a semiconductor substrate 1 made of silicon.
The N channel MOS device 11 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over a P well 4 formed of a p-type doped layer diffused in the semiconductor substrate 1, and also with a source 6 and a drain 7, formed of a heavily doped n-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The P channel MOS device 12 is provided with a gate oxide film 2 and gate electrode 3 formed on the surface of the semiconductor substrate 1 over an N well 5 formed of an n-type doped layer diffused in the semiconductor substrate 1, and also with a source 16 and a drain 17, formed of a heavily doped p-type layer on the surface of the semiconductor substrate 1, matching the gate electrode 3.
The MONOS device 35 is provided with a memory insulating film 34 comprising a memory oxide film 31, a memory nitride film 32, and a top oxide film 33, and also with a memory gate electrode 50, which are all formed on the surface of the semiconductor substrate 1 over a P well 4 formed of a p-type doped layer diffused in the semiconductor substrate 1, and also with a source 7 (for common use as the drain 7 of the N channel MOS device 11) and a drain 18, formed of a heavily doped n-type layer on the surface of the semiconductor substrate 1, matching the memory gate electrode 50.
The P channel MOS device 12, N channel MOS device 11, and MONOS device 35 are isolated from each other with field oxide films 13 formed on the surface of the semiconductor substrate.
An interlevel insulator 8 is formed on the entire surface of the semiconductor substrate 1 and via contact holes 9 formed in the interlevel insulator 8, connection to other MOS devices formed on the semiconductor substrate 1 is made with interconnections 10, ends of which are connected to the gate electrodes 3, the sources 6, 16 and the drains 7, 17, 18 of the respective semiconductor devices 11, 12, and 35.
A method of fabricating the semiconductor device shown in FIG. 71 is described hereinafter with reference to FIGS. 72 through 76, which are cross-sectional views showing respective steps of a fabrication process.
The first half of the fabrication process of the semiconductor device described above comprises the same steps as those of a third embodiment of a method of fabricating a semiconductor device according to the invention as described hereinafter with reference to FIGS. 29 through 34. Accordingly, illustration of these steps is omitted, and the fabrication process is described with reference to FIG. 72 only.
First, by oxidizing the semiconductor substrate 1 made of silicon in an oxidizing atmosphere, an oxide film is formed on the surface thereof
Subsequently, a photo-resist which is a photosensitive polymer is formed on the entire surface of the oxide film by use of a spin coater, and by applying exposure and development treatment thereto with the use of a predetermined mask, the photo-resist is patterned in such a way as to form an opening delineating an N channel region where the N channel MOS device and the MONOS device are to be formed. Thereafter, the oxide film is etched by use of the photo-resist as an etching mask.
Then, a first buffer oxide film is formed by oxidizing the semiconductor substrate 1 in an oxidizing atmosphere, whereupon ions of boron, a p-type dopant, are implanted to form a P well. As a result, boron is implanted in the surface region of the semiconductor substrate 1, in the N channel region 42 where the first buffer oxide film with a thin oxide film is formed.
Subsequently, after removing the oxide film described in the foregoing and the first buffer oxide film, a second buffer oxide film is formed on the entire surface of the semiconductor substrate 1 by oxidizing the same in an oxidizing atmosphere, and the photo-resist is patterned in such a way as to form an opening delineating a P channel region 43 where the P channel MOS device is to be formed.
Ions of phosphorus, an n-type dopant, are implanted into the P channel region 43 with the use of the photo-resist described above as a mask against ion implantation. The second buffer oxide film is then removed.
Thereafter, by oxidizing the semiconductor substrate 1 in a thin oxidizing atmosphere and applying heat treatment thereto, the ion-implanted dopants are activated, thereby forming the P well 4 and an N well 5, and at the same time, a pad oxide film is formed on the surface of the semiconductor substrate 1.
Subsequently, on the entire surface of the pad oxide film, a nitride film composed of a silicon nitride film is formed by means of the chemical vapor deposition process, and a photo-resist is formed in regions where the N channel MOS device, P channel MOS device, and MONOS device are to be formed, respectively.
The nitride film is then etched using the photo-resist described above as an etching mask.
Thereafter, field oxide films 13 shown in FIG. 72 are formed through selective oxidation in an oxidizing atmosphere, and the nitride film as well as the pad oxide film are removed.
As shown in FIG. 72, gate oxide films 2 are then formed through oxidation in an oxidizing atmosphere, and a first gate electrode material 48 is formed over the gate oxide films 2.
Then, photo-resists 113 are patterned in regions where the gate electrodes are to be formed. The first gate electrode material 48 is etched using the photo-resists 113 as etching masks, forming the gate electrodes 3 as shown in FIG. 73. Further, the gate oxide film 2 except portions thereof underneath the gate electrodes 3 is removed.
Thereafter, through oxidation in an oxidizing atmosphere, the memory oxide film 31 shown in FIG. 74 is formed and turned into a nitride oxide film by annealing in an ammonia atmosphere.
In the course of annealing in an ammonia atmosphere, ammonia and hydrogen are diffused into the gate oxide films 2, a constituent part of the MOS devices already formed, causing a problem of positive electric charge being induced in the gate oxide films 2 and at the interface between the gate oxide films 2 and the semiconductor substrate 1.
Since the electric charge remains without electrical neutrality being restored before completion of the fabrication process, there will arise a problem that shift in the threshold voltage of the respective MOS devices occurs.
Subsequently, on the entire surface of the memory oxide film 31, the memory nitride film 32, the top oxide film 33, and the second gate electrode material 49 are formed in sequence.
Thereafter, photo-resist 114 is patterned in a region where the memory gate electrode of the MONOS device is to be formed.
The second gate electrode material 49, the top oxide film 33, the memory nitride film 32, and the memory oxide film 31 are etched using the photo-resist 114 as an etching mask, forming the memory gate electrode 50 as shown in FIG. 75.
Then, ions of arsenic, an n-type dopant, are implanted into the surface of the semiconductor substrate 1, in parts of the N channel region 42, matching the gate electrode 3, and the memory gate electrode 50, forming the source 6 and the drains 7, belonging to a heavily doped N layer as shown in FIG. 76.
Subsequently, ions of boron, a p-type dopant, are implanted into the surface of the semiconductor substrate 1, in part of the P channel region 43 shown in FIG. 75, matching the gate electrode 3, forming the source 16 and the drain 17 belonging to a heavily doped P layer as shown in FIG. 76. Thereafter, heat treatment is applied thereto in order to activate the dopants.
Further, an interlevel insulator 8 is formed on the entire surface as shown in FIG. 76, openings for the contact holes 9 are formed in the interlevel insulator 8, and the interconnections 10 is provided.
Thus, using the semiconductor substrate 1 made of silicon, the semiconductor device comprising the N channel MOS device 11, the P channel MOS device 12, and the MONOS device 35, which are formed on the same semiconductor substrate 1, is fabricated.
There are cases where MOS devices of the aforesaid structure are used in the controller of a satellite sent up into space, or the controller of a nuclear reactor.
However, when the conventional MOS devices described above are put to use in an environment where radiation such as gamma rays are present, positive electric charge is developed in the gate oxide films, or at the interface between the semiconductor substrate and the gate oxide films, lowering the threshold voltage of the N channel MOS device, and generating leakage current.
On the other hand, this will raise the threshold voltage of the P channel MOS device, rendering the controller inoperative.
Also, when fabricating a semiconductor device comprising the N channel MOS device, the P channel MOS device, and the MONOS device, all formed on a semiconductor substrate made of silicon, the memory oxide film is turned into a nitride oxide film by applying heat treatment thereto in an ammonia atmosphere in order to improve the writable and erasable characteristic of the MONOS device. At this point in time, positive electric charge is induced in the gate oxide films and at the interface between the gate oxide films and the semiconductor substrate as described in the foregoing due to the reaction of ammonia and hydrogen, creating a cause for malfunction due to shift in the threshold voltage.
It is therefore an object of the invention to inhibit shift in the threshold voltage of MOS devices in a radiation environment, and another object of the invention is to inhibit shift in the threshold voltage of MOS devices which occurs when annealing in an ammonia atmosphere during a process of fabricating a semiconductor device comprising MOS devices and a MONOS device, formed on the semiconductor substrate, by solving the problems described in the foregoing.
To this end, a semiconductor device according to the invention has the structures described as follows:
The semiconductor device comprises a semiconductor substrate, and an N channel MOS device and a P channel MOS device having a gate insulating film formed on the semiconductor substrate and a gate electrode formed on the gate insulating film, the gate insulating film being made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film and a gate silicon nitride film respectively.
Or, in a semiconductor device comprising an SOI substrate made up of a supporting substrate, an insulating film, and a plurality of semiconductor layers, each patterned in an island-like shape, and an N channel MOS device and a P channel MOS device having a gate insulating film formed on each of the semiconductor layers, and a gate electrode formed on the gate insulating film, respectively, the gate insulating film may be made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film, and a gate silicon nitride film.
These semiconductor devices may further comprise a MONOS device having a memory insulating film composed of a memory oxide film, a memory nitride film, and a top oxide film, formed on the semiconductor substrate, and a memory gate electrode formed on the memory insulating film.
Further the gate insulating film of the N channel MOS device is made up of a gate oxide film composed of a silicon dioxide film, and only the gate insulating film of the P channel MOS device is made up of a dual-layer film consisting of a gate oxide film composed of a silicon dioxide film, and a gate silicon nitride film.
The method of fabricating a semiconductor device according to the invention comprises the following steps (1) to (18) to accomplish the object of the invention:
(1) step of forming an oxide film on the entire surface of a semiconductor substrate through oxidation thereof in an oxidizing atmosphere;
(2) step of etching the oxide film on the semiconductor substrate, in a N channel region where an N channel MOS device is to be formed;
(3) step of forming a first buffer oxide film for implanting a p-type dopant into the N channel region;
(4) step of implanting the p-type dopant into the N channel region of the semiconductor substrate;
(5) step of forming a second buffer oxide film on the entire surface of the semiconductor substrate after etching the oxide film formed on the entire surface of the semiconductor substrate;
(6) step of implanting an n-type dopant into a P channel region of the semiconductor substrate, where a P channel MOS device is to be formed, using photosensitive polymer as a mask;
(7) step of forming a pad oxide film on the entire surface of the semiconductor substrate after etching the second buffer oxide film, and activating the respective dopants implanted in an oxidizing atmosphere;
(8) step of forming a nitride film composed of a silicon nitride film, on the pad oxide film;
(9) step of etching the nitride film in regions of the semiconductor substrate where field oxide films are to be formed;
(10) step of removing the nitride film and pad oxide film after forming the field oxide films on the semiconductor substrate by means of a selective oxidation method for effecting device isolation between the N channel region and the P channel region;
(11) step of forming a gate oxide film on the entire surface of the semiconductor substrate, in the N channel region and P channel region, in an oxidizing atmosphere, forming a gate silicon nitride film on the entire surface of the gate oxide film, and forming a gate electrode material on the entire surface of the gate silicon nitride film;
(12) step of forming gate electrodes by etching the gate electrode material and the gate silicon nitride film;
(13) step of forming a highly doped n-type layer in regions for forming a source and drain, in the N channel region of the semiconductor substrate, using photosensitive polymer as a mask against ion implantation;
(14) step of forming a highly doped p-type layer in regions for forming a source and drain, in the P channel region of the semiconductor substrate, using photosensitive polymer as a mask against ion implantation;
(15) step of forming an interlayer insulating film composed primarily of a silicon dioxide film on the entire surface of the semiconductor substrate;
(16) step of activating the highly doped n-type and p-type layers by annealing thereto, and step of forming a plurality of contact holes in the interlayer insulating film by means of the photo-etching method; and
(17) step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device and the P channel MOS device, respectively.
Further, the following steps may be included instead of the aforementioned steps (11) and (12):
step of forming a gate oxide film on the entire surface of the semiconductor substrate, in the N channel region and P channel region in an oxidizing atmosphere, forming a gate silicon nitride film on the entire surface of the gate oxide film;
step of removing the gate silicon nitride film by photo-etching such that the gate silicon nitride film in the N channel region is left intact;
step of forming a gate electrode material on the entire surface of the semiconductor substrate; and
step of forming gate electrodes by etching the gate electrode material.
Further, in the case of fabricating the semiconductor device provided with a MONOS semiconductor device, it comprises the following steps instead of the aforementioned steps (11) and (12)
step of forming a gate oxide film on the entire surface of the semiconductor substrate, in the N channel region and the P channel region, in an oxidizing atmosphere, and forming a gate silicon nitride film on the entire surface of the gate oxide film;
step of forming a first gate electrode material on the entire surface of the gate silicon nitride film, and forming gate electrodes by a photo-etching method;
step of forming a memory oxide film by oxidizing the entire surface of the semiconductor substrate in an oxidizing atmosphere, and turning the memory oxide film into an nitride oxide film by annealing in an ammonia atmosphere;
step of forming a memory nitride film on the memory oxide film, forming a top oxide film by oxidizing the memory nitride film in an oxidizing atmosphere, and forming a second gate electrode material on the entire surface of the top oxide film;
step of forming a memory gate electrode by photo-etching the second gate electrode material, the top oxide film, the memory nitride film, and the memory oxide film; and
step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device, the P channel MOS device, and a MONOS device, respectively in the aforementioned step (17).
In the case of using an SOI substrate made up of a supporting substrate an insulating film and the semiconductor layer, the following steps (1) to (14) are included:
(1) step of forming a first semiconductor layer patterned in an island-like shape on which an N channel MOS device is to be formed, and a second semiconductor layer patterned in an island-like shape on which a P channel MOS device is to be formed, by etching the semiconductor layer on the SOI substrate using the photosensitive polymer as an etching mask;
(2) step of forming a gate oxide film on the surface of the first and second semiconductor layers, respectively, by oxidizing the respective semiconductor layers in an oxidizing atmosphere;
(3) step of forming a P channel doped layer in the region of the first semiconductor layer using photosensitive polymer as a mask against ion implantation;
(4) step of forming an N channel doped layer in the region of the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(5) step of forming a p-type doped layer for prevention of surface inversion in the boundary region surrounding the first semiconductor layer using photosensitive polymer as a mask against ion implantation;
(6) step of forming an n-type doped layer for prevention of surface inversion in the boundary region surrounding the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(7) step of forming a gate silicon nitride film on the gate oxide film formed on the surface of the respective semiconductor layers and forming a gate electrode material on the gate silicon nitride film;
(8) step of forming gate electrodes by etching the gate electrode material and the gate silicon nitride film.
(9) step of forming a highly doped n-type layer in regions of the first semiconductor layer, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(10) step of forming a highly doped p-type layer in regions of the second semiconductor layer, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(11) step of forming an interlayer insulating film composed primarily of a silicon dioxide film on the entire surfaces of the semiconductor layers;
(12) step of activating the highly doped n-type and p-type layers by annealing;
(13) step of forming a plurality of contact holes in the interlayer insulating film by means of a photo-etching method; and
(14) step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device and the P channel MOS device, respectively.
The following steps may be included instead of the aforementioned steps (7) and (8):
step of forming a gate silicon nitride film on the gate oxide film formed on the surface of the respective semiconductor layers;
step of removing the gate silicon nitride film by the photo-etching method except that the region of the first semiconductor layer is kept intact;
step of forming a gate electrode material on the entire surfaces of the semiconductor layers; and
step of forming gate electrodes by etching the gate electrode material.
Still further, in the case of fabricating a semiconductor device provided with a MOS semiconductor device and a MONOS semiconductor device using an SOI substrate made up of a supporting substrate, an insulating film and a semiconductor layer, the following steps (1) to (17) are included:
(1) step of forming photosensitive polymer on the semiconductor layer of the SOI, and forming a first semiconductor layer patterned in an island-like shape on which an N channel MOS device is to be formed, a second semiconductor layer patterned in an island-like shape on which a P channel MOS device is to be formed, and a third semiconductor layer patterned in an island-like shape on which a MONOS device is to be formed, by etching the semiconductor layer using the photosensitive polymer as an etching mask;
(2) step of forming a gate oxide film on the surface of the first through third semiconductor layers, respectively, by oxidizing the respective semiconductor layers in an oxidizing atmosphere;
(3) step of forming a P channel doped layer in the regions of the first and the third semiconductor layers using photosensitive polymer as a mask against ion implantation;
(4) step of forming an N channel doped layer in the region of the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(5) step of forming a p-type doped layer for prevention of surface inversion in the boundary regions surrounding the first and the third semiconductor layers using photosensitive polymer as a mask against ion implantation;
(6) step of forming an n-type doped layer for prevention of surface inversion in the boundary region surrounding the second semiconductor layer using photosensitive polymer as a mask against ion implantation;
(7) step of forming a gate silicon nitride film on the entire surfaces of the semiconductor layers;
(8) step of forming a first gate electrode material on the entire surface of the gate silicon nitride film, and forming gate electrodes by means of a photo-etching method;
(9) step of forming a memory oxide film by oxidizing the entire surface of the semiconductor layers in an oxidizing atmosphere, and annealing in an ammonia atmosphere for turning the memory oxide film into a nitride oxide film;
(10) step of forming a memory nitride film on the memory oxide film, forming a top oxide film by oxidizing the memory nitride film in an oxidizing atmosphere, and forming a second gate electrode material on the top oxide film;
(11) step of forming a memory gate electrode by etching the second gate electrode material, the top oxide film, the memory nitride film, and the memory oxide film by means of the photo-etching method;
(12) step of forming a highly doped n-type layer in regions of the first and third semiconductor layers, respectively, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(13) step of forming a highly doped p-type layer in regions of the second semiconductor layer, for forming a source and a drain, using photosensitive polymer as a mask against ion implantation;
(14) step of forming an interlayer insulating film composed primarily of a silicon dioxide film on the entire surfaces of the semiconductor layers;
(15) step of activating the highly doped n-type and p-type layers by annealing;
(16) step of forming a plurality of contact holes in the interlayer insulating film by means of the photo-etching method; and
(17) step of forming interconnections connected, via the contact holes, to the gate electrode, the source, and the drain of the N channel MOS device, the P channel MOS device, and the MONOS device, respectively.
As described above, in the semiconductor device and the method of fabricating the same, according to the invention, the gate insulating film of the N channel MOS device and the P channel MOS device, respectively, or the gate insulating film of the P channel MOS device only, is made up of the dual-layer film consisting of the gate oxide film composed of the silicon dioxide film, and gate silicon nitride film.
As a result, diffusion of reacting gas such as ammonia and hydrogen is inhibited in the course of heat treatment in an ammonia atmosphere during the fabrication process owing to the effect of the gate silicon nitride film which is a closely packed film, making up the gate insulation film.
Consequently, reaction in the gate oxide film, and at the interface between the gate oxide films and semiconductor substrate can be inhibited with the result that generation of positive electric charge in these regions is prevented, thereby inhibiting shift in the threshold voltage.
Further, since the gate insulating film is made up of the dual-layer film consisting of the gate oxide film composed of the silicon dioxide film and the gate silicon nitride film, there will arise a matching problem at the interface between the gate oxide film and the gate silicon nitride film with the result that an electrically charged interfacial energy level occurs at the interface.
In the MOS devices of the invention, the threshold voltage is controlled by regulating the concentration of dopants in the wells to cope with the interfacial energy level.
Hence, when the semiconductor device according to the invention is put to use in a radiation environment, positive electric charge generated by the presence of gamma rays or the like decreases in magnitude due to the effect of the interfacial energy level, thereby inhibiting shift in the threshold voltage.
The above and other objects, features and advantages of the invention will be apparent from the following detailed description which is to be read in conjunction with the accompanying drawings.